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Job Title Job Type Work Place Operation

Job Description:

Work with Front-End design team and physical design team for super large-scale SoC chip physical implementation from RTL to GDS. Focus on physical design of deep sub-micron ultra large chip including block and chip level synthesis, floorplan, place and route, timing closure, physical verification, EM/IR signoff checks etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team.

Job Requirements:

1、 Hands on experience in super large-scale SoC chip physical design, especially experience in 7nm FinFet technology and high-speed design implementation.

2、 Solid knowledge and rich experience on synthesis, floorplan, place, CTS and routing, static timing analysis, EM/IR-drop and physical verification.

3、 Project experience on hierarchical flow such as top-level partition, timing budgeting, pin assignment and Power Network Planning etc.

4、 Expertise with Synopsys/Cadence/Mentor EDA tools.

5、 Familiar with Unix/Linux environment and good at scripts.

6、 A high-level of self-motivation and a proactive approach to solving problems.

7、 Good communication skills, strong interpersonal skills and the flexibility.

8、 Dedicated, hardworking, and good team player.

Job Description:

Work with Front-End design team and physical design team for super large-scale SoC chip physical implementation from RTL to GDS. Focus on physical design of deep sub-micron ultra large chip including block and chip level synthesis, floorplan, place and route, timing closure, physical verification, EM/IR signoff checks etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team.

Job Requirements:

1、 Hands on experience in super large-scale SoC chip physical design, especially experience in 7nm FinFet technology and high-speed design implementation.

2、 Solid knowledge and rich experience on synthesis, floorplan, place, CTS and routing, static timing analysis, EM/IR-drop and physical verification.

3、 Project experience on hierarchical flow such as top-level partition, timing budgeting, pin assignment and Power Network Planning etc.

4、 Expertise with Synopsys/Cadence/Mentor EDA tools.

5、 Familiar with Unix/Linux environment and good at scripts.

6、 A high-level of self-motivation and a proactive approach to solving problems.

7、 Good communication skills, strong interpersonal skills and the flexibility.

8、 Dedicated, hardworking, and good team player.

Job Description:

Work with Front-End design team and physical design team for super large-scale SoC chip physical implementation from RTL to GDS. Focus on physical design of deep sub-micron ultra large chip including block and chip level synthesis, floorplan, place and route, timing closure, physical verification, EM/IR signoff checks etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team.

Job Requirements:

1、 Hands on experience in super large-scale SoC chip physical design, especially experience in 7nm FinFet technology and high-speed design implementation.

2、 Solid knowledge and rich experience on synthesis, floorplan, place, CTS and routing, static timing analysis, EM/IR-drop and physical verification.

3、 Project experience on hierarchical flow such as top-level partition, timing budgeting, pin assignment and Power Network Planning etc.

4、 Expertise with Synopsys/Cadence/Mentor EDA tools.

5、 Familiar with Unix/Linux environment and good at scripts.

6、 A high-level of self-motivation and a proactive approach to solving problems.

7、 Good communication skills, strong interpersonal skills and the flexibility.

8、 Dedicated, hardworking, and good team player.

Position Description:

For this role we are looking for engineers who are capable of co-working, innovating, and contributing to a global verification team focused on SoC verification design across various layers of verification scope and approaches, through all phases of the verification flow. The engineer will work in SiEngine SoC verification team in Shanghai or Beijing.

Main Responsibility:

1、 Contributing to development of test plans and testbench documentation.

2、 Contributing to development of test plans and testbench documentation.

3、 Contributing to development of test plans and testbench documentation.

4、 Participation in system-level verification such as FPGA or emulation efforts.

5、 Joint review on design specification, verification coding, and coverage metrics.

Required Skills and Experiences:

1、 M.Sc. or Ph.D. degree from China top universities (211 is a must, 985 is preferred) with major on Computer Science, EE or Automation etc.

2、 Good academic record with GPA>3.7 and top 10% rank in the major.

3、 Proficiency in HDL and scripting languages, e.g. Verilog, Perl, TCL, Python.

4、Knowledge of assembly language (preferably ARM), and/or C/C++.

5、 Ready to express ideas with excellent interpersonal and communication skills, good teamwork adaptability, good oral and written English skills, energetic and self-motivated.

6、 Prepared to be assigned to tasks across the full range of your skills and experience.

7、Willingness to be flexible and accept new challenges.

8、 Ability to schedule own workload and plan tasks effectively.

9、 Graduate in spring/summer of 2020.

Position Description:

For this role we are looking for engineers who are capable of co-working, innovating, and contributing to a global verification team focused on SoC verification design across various layers of verification scope and approaches, through all phases of the verification flow. The engineer will work in SiEngine SoC verification team in Shanghai or Beijing.

Main Responsibility:

1、 Contributing to development of test plans and testbench documentation.

2、 Contributing to development of test plans and testbench documentation.

3、 Contributing to development of test plans and testbench documentation.

4、 Participation in system-level verification such as FPGA or emulation efforts.

5、 Joint review on design specification, verification coding, and coverage metrics.

Required Skills and Experiences:

1、 M.Sc. or Ph.D. degree from China top universities (211 is a must, 985 is preferred) with major on Computer Science, EE or Automation etc.

2、 Good academic record with GPA>3.7 and top 10% rank in the major.

3、 Proficiency in HDL and scripting languages, e.g. Verilog, Perl, TCL, Python.

4、Knowledge of assembly language (preferably ARM), and/or C/C++.

5、 Ready to express ideas with excellent interpersonal and communication skills, good teamwork adaptability, good oral and written English skills, energetic and self-motivated.

6、 Prepared to be assigned to tasks across the full range of your skills and experience.

7、Willingness to be flexible and accept new challenges.

8、 Ability to schedule own workload and plan tasks effectively.

9、 Graduate in spring/summer of 2020.

Position Description:

For this role we are looking for engineers who are capable of co-working, innovating, and contributing to a global verification team focused on SoC verification design across various layers of verification scope and approaches, through all phases of the verification flow. The engineer will work in SiEngine SoC verification team in Shanghai or Beijing.

Main Responsibility:

1、 Contributing to development of test plans and testbench documentation.

2、 Contributing to development of test plans and testbench documentation.

3、 Contributing to development of test plans and testbench documentation.

4、 Participation in system-level verification such as FPGA or emulation efforts.

5、 Joint review on design specification, verification coding, and coverage metrics.

Required Skills and Experiences:

1、 M.Sc. or Ph.D. degree from China top universities (211 is a must, 985 is preferred) with major on Computer Science, EE or Automation etc.

2、 Good academic record with GPA>3.7 and top 10% rank in the major.

3、 Proficiency in HDL and scripting languages, e.g. Verilog, Perl, TCL, Python.

4、Knowledge of assembly language (preferably ARM), and/or C/C++.

5、 Ready to express ideas with excellent interpersonal and communication skills, good teamwork adaptability, good oral and written English skills, energetic and self-motivated.

6、 Prepared to be assigned to tasks across the full range of your skills and experience.

7、Willingness to be flexible and accept new challenges.

8、 Ability to schedule own workload and plan tasks effectively.

9、 Graduate in spring/summer of 2020.

Position Description:

Siengine Platform Hardware team is seeking an experienced engineer to develop silicon development board and customer evaluation board for Siengine Automotive IVI/eCockpit SoC products. This position needs candidate to have solid PCBA and system level hardware design knowledge and experience. The candidate will be co-working with IC design, software, validation teams on the full cycle of SoC product development.

The major tasks for this position include but not limited to: system requirement analysis and feasibility evaluation, hardware spec, hardware architecture design, component selection, schematic design, support for PCB placement and layout review, DFMEA analysis, release BOM, NPI build support, system bring-up, debug, validation, till to production.

Job Requirements:

1、 7+ years of electrical design experience in automotive IVI/ecockpit system, mobile, or x86 system.

2、 Rich experience of trouble shooting in product verification and validation.

3、 Skilled with EDA tools (Allegro). Skilled with lab equipment for debugging.

4、 Good knowledge of signal integrity and power integrity. Hand on experience with LPDDR4/4x, PCIe, Display Port, MIPI-DSI/CSI, USB3 and UFS design.

5、 Bachelor or above degree of Electrical Engineering, Automotive Engineering or related area.

6、 Experience of Samsung, Qualcomm, Renesas, NXP automotive platform development is a plus.

7、 Familiar with any of the following processors architecture: arm, x86 or PowerPC. Prefer to have multi-core knowledge.

8、 Knowledge of ISO 26262 and function safety is a plus.

Job Description:

Lead or co-lead the team to achieve verification target of state-of-the-art ARM based SoC, or one of its sub-system. Be responsible for verification quality and schedule.

1、Lead the verification process, decompose tasks for each team member.

2、Create verifcation plan and review with architecture/design team.

3、Create random constraint test bench based on the requirement.

4、Create random test cases and direct test cases to achieve coverage goals.

5、Work closely with architecture/design team to identify problems.

6、Low-power verification.

7、Performance verification.

8、Finish verification tasks on time.

  2. Job Requirements:

1、 Bachelor or above with more than 5 years’ work experience.

2、 Proficient with System Verilog & UVM.

3、 Expert in the use of Cadence/Synopsys verification tools.

4、 Verification experience on automotive chip is a great plus.

5、 CPU/GPU/ISP/DDR architecture knowledge is a great plus.

6、 high speed interface protocol knowledge is a great plus: PCIe/USB3.1/Ethernet, etc.

verification experience using Palladium/ZeBU is a great plus.

scripting languages (Python, Perl, Makefile, …) is an additional plus.

C and ARMv8.x assembly code programming skill is an additional plus.

Good communication skills.

Job Description:

Lead or co-lead the verification team to finish latest ARM Cortex-M or Cortes-R based MCU verification, or subsystem level verification. Take charge of verification quality and schedule.

1、1.Lead the verification process, decompose tasks for each team member.

2、Create test plan and review with architecture/design team.

3、Create random constraint test bench based on the requirement.

4、Create random test cases and direct test cases to achieve coverage goals.

5、Work closely with architecture/design team to identify problems.

6、Low-power verification.

7、Automotive function safety (ISO26262) verification.

8、Performance verificatio.

9、Finish verification tasks on time.

Job Requirements:

1、 Bachelor or above with 6~10+ years’ work experience.

2、 Proficient with System Verilog & UVM.

3、 Expert in the use of Cadence/Synopsys verification tools.

4、 verification experience on automotive chip is a great plus.

5、 verification experience on automotive chip is a great plus.

6、 EFLASH Controller knowledge is a great plus.

7、 Interface protocol knowledge is a great plus: USB3.1/Ethernet/CAN_FD/LIN, etc.

8、 Automotive function safety (ISO26262) verification experience is a great plus.

9、 verification experience using FPGA is a plus.

10、scripting languages (Python, Perl, Makefile, …) is an additional plus.

11、 C and ARMv7.x or ARMv8.x assembly code programming skill is an additional plus.

12、 Good communication skills.

Job Description:

This position is for a digital-MCU design engineer to build next-gen automotive MCU chipsets.As part of the MCU design team, the design engineer will mainly focus on following areas, but not limited to:

1、Prepare micro-architecture specification for IP or subsystem design.

2、Provide detailed technical documentation with specifications, block diagrams, and requirements to stakeholders.

3、RTL coding to verify against circuit implementation; Perform integration into MCUs.

4、Module level Automotive functional safety related design and document.

5、Maintain the 3rd party IP from vendor and verify functions by creating test cases.

6、Module level synthesize with sdc/upf; support chip level synthesis as IP owner.

7、Assist with chip bring up and perform silicon/FPGA functional/performance validation.

8、Assist with automotive functional safety (ISO26262) certification.

9、Define timing and power specifications and identify timing solutions.

10、Assist with backend team on perform place-and-route and timing analysis of modules.

Job Requirements:

1、 Master’s degree with at least 5 years’ experience in digital design.

2、 Proven track record for successful design of IC products in the past.

3、 Good background in C, Verilog, SystemVerilog and verification methodology.

4、 Knowledge and experience with Python/Tcl and Unix/Linux Makefile scripting strongly desired.

5、 A high-level of self-motivation and a proactive approach to solving problems.

6、 A high-level of self-motivation and a proactive approach to solving problems.

7、 Familiar with the frontend ASIC design methodology/flow.

Solid knowledge in one of the following areas is a plus:

1、 Knowledge of ARM cortex M or cortex R's MCU or SOC architecture.

2、 Knowledge of automotive function safety (ISO26262) design.

3、 Knowledge of security design.

4、 Knowledge of low power design.

5、 Knowledge or design experience of CAN_FD/LIN/USB/Ethernet/UFS/eMMC/EFALSH Controller.

Job Description:

This position is for a digital-MCU design engineer to build next-gen automotive MCU chipsets.As part of the MCU design team, the design engineer will mainly focus on following areas, but not limited to:

1、Prepare micro-architecture specification for IP or subsystem design.

2、Provide detailed technical documentation with specifications, block diagrams, and requirements to stakeholders.

3、RTL coding to verify against circuit implementation; Perform integration into MCUs.

4、Module level Automotive functional safety related design and document.

5、Maintain the 3rd party IP from vendor and verify functions by creating test cases.

6、Module level synthesize with sdc/upf; support chip level synthesis as IP owner.

7、Assist with chip bring up and perform silicon/FPGA functional/performance validation.

8、Assist with automotive functional safety (ISO26262) certification.

9、Define timing and power specifications and identify timing solutions.

10、Assist with backend team on perform place-and-route and timing analysis of modules.

Job Requirements:

1、 Master’s degree with at least 5 years’ experience in digital design.

2、 Proven track record for successful design of IC products in the past.

3、 Good background in C, Verilog, SystemVerilog and verification methodology.

4、 Knowledge and experience with Python/Tcl and Unix/Linux Makefile scripting strongly desired.

5、 A high-level of self-motivation and a proactive approach to solving problems.

6、 A high-level of self-motivation and a proactive approach to solving problems.

7、 Familiar with the frontend ASIC design methodology/flow.

Solid knowledge in one of the following areas is a plus:

1、 Knowledge of ARM cortex M or cortex R's MCU or SOC architecture.

2、 Knowledge of automotive function safety (ISO26262) design.

3、 Knowledge of security design.

4、 Knowledge of low power design.

5、 Knowledge or design experience of CAN_FD/LIN/USB/Ethernet/UFS/eMMC/EFALSH Controller.

Job Description:

This position is for a digital-MCU design engineer to build next-gen automotive MCU chipsets.As part of the MCU design team, the design engineer will mainly focus on following areas, but not limited to:

1、Prepare micro-architecture specification for IP or subsystem design.

2、Provide detailed technical documentation with specifications, block diagrams, and requirements to stakeholders.

3、RTL coding to verify against circuit implementation; Perform integration into MCUs.

4、Module level Automotive functional safety related design and document.

5、Maintain the 3rd party IP from vendor and verify functions by creating test cases.

6、Module level synthesize with sdc/upf; support chip level synthesis as IP owner.

7、Assist with chip bring up and perform silicon/FPGA functional/performance validation.

8、Assist with automotive functional safety (ISO26262) certification.

9、Define timing and power specifications and identify timing solutions.

10、Assist with backend team on perform place-and-route and timing analysis of modules.

Job Requirements:

1、 Master’s degree with at least 5 years’ experience in digital design.

2、 Proven track record for successful design of IC products in the past.

3、 Good background in C, Verilog, SystemVerilog and verification methodology.

4、 Knowledge and experience with Python/Tcl and Unix/Linux Makefile scripting strongly desired.

5、 A high-level of self-motivation and a proactive approach to solving problems.

6、 A high-level of self-motivation and a proactive approach to solving problems.

7、 Familiar with the frontend ASIC design methodology/flow.

Solid knowledge in one of the following areas is a plus:

1、 Knowledge of ARM cortex M or cortex R's MCU or SOC architecture.

2、 Knowledge of automotive function safety (ISO26262) design.

3、 Knowledge of security design.

4、 Knowledge of low power design.

5、 Knowledge or design experience of CAN_FD/LIN/USB/Ethernet/UFS/eMMC/EFALSH Controller.

Job Description:

1、Work with an experienced design team to design analog block for automotive SOC or MCU.

2、Responsible for analog design, simulation, layout supervision, tape out and silicon verification.

3、Work closely with design validation and characterization team to support successful product release.

4、Experience on GPIO, ADC, DAC, Regulator(DCDC or LDO) design skill is a plus.

5、Candidates must be self-motivated, driven and hard workin.

Job Requirements:

1、 Integrated circuit/ electronic engineering major, master degree or above.

2、 2-3yr direct experience in analog IC design.

3、 experience or related course work in the following fields.

4、 Deep knowledge of analog circuit design.

5、 Power-Management design and Ultra-Low-Power Analog Design.

6、 Good communication skill is required.

7、 Self-driven and proactive.

8、 Good English communication skill, good team work.

Job Description:

1、Work with an experienced design team to design analog block for automotive SOC or MCU.

2、Responsible for analog design, simulation, layout supervision, tape out and silicon verification.

3、Work closely with design validation and characterization team to support successful product release.

4、Experience on GPIO, ADC, DAC, Regulator(DCDC or LDO) design skill is a plus.

5、Candidates must be self-motivated, driven and hard workin.

Job Requirements:

1、 Integrated circuit/ electronic engineering major, master degree or above.

2、 2-3yr direct experience in analog IC design.

3、 experience or related course work in the following fields.

4、 Deep knowledge of analog circuit design.

5、 Power-Management design and Ultra-Low-Power Analog Design.

6、 Good communication skill is required.

7、 Self-driven and proactive.

8、 Good English communication skill, good team work.

Job Description:

1、Work with an experienced design team to design analog block for automotive SOC or MCU.

2、Responsible for analog design, simulation, layout supervision, tape out and silicon verification.

3、Work closely with design validation and characterization team to support successful product release.

4、Experience on GPIO, ADC, DAC, Regulator(DCDC or LDO) design skill is a plus.

5、Candidates must be self-motivated, driven and hard workin.

Job Requirements:

1、 Integrated circuit/ electronic engineering major, master degree or above.

2、 2-3yr direct experience in analog IC design.

3、 experience or related course work in the following fields.

4、 Deep knowledge of analog circuit design.

5、 Power-Management design and Ultra-Low-Power Analog Design.

6、 Good communication skill is required.

7、 Self-driven and proactive.

8、 Good English communication skill, good team work.

Staff Style

Elite managers in the industry closely work together in SiEngine

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